1. Technical Field
This invention relates generally to memory arrays, and more particularly, to a method of matching characteristics of core and reference cells of the array.
2. Background Art
FIG. 1 illustrates a portion of a NOR memory cell array 20. The array 20 includes individual memory cells C1, C2, C3, . . . C32 made up of respective MOS field effect transistors T1, T2, T3, . . . T32, the transistors including a source S, a drain D, a floating gate FG, and a control gate CG. Bit lines B0, B1, B2, . . . B7 and word lines W0, W1, W2, W3 are included, as is well known. The cells C1-C32 are connected in an army of rows 22, 24, 26, 28 and columns 30, 32, 34, 36, 38, 40, 42, 44, with the control gates CG of the cells in a row (for example row 24) being connected to a respective word line (W1) and the drains D of the cells in a column (for example column 38) being connected to a respective bit line (B4). The sources S of the cells in a column are connected together, and are connected to the sources S of the cells of other columns by conductive lines (one shown at 46). Approximately every 20 bit lines across the array 20, each conductive line 46 connects to a contact (two shown at 48, 50) to which a voltage is supplied, to in turn supply a voltage to the source S of each cell.
A cell of the array 20 can be programmed by applying programming voltage (for example 9-10 volts) to the control gate CG, approximately 5 volts to the bit line to which the drain D is connected, and applying a voltage Vss (for example ground) to the associated contacts 48, 50. These voltages cause hot electrons to be injected from the drain depletion region of the transistor of the cell into the floating gate FG. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate FG and create a negative charge therein that increases the threshold of the cell to a value in excess of approximately 4 volts.
A cell can be read by applying a voltage of for example approximately 5 volts to the control gate CG, applying approximately 1 volt to the bit line to which the drain D is connected, and applying for example ground to the Vss contacts 48, 50, and sensing the bit line current. If a cell is programmed and the threshold voltage is relatively high (4 volts), the current through the transistor will be zero or relatively low. If the cell is not programmed or is erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the current through the transistor will be relatively high.
A cell can be erased in several ways. In one approach, applying a relatively high voltage, typically 12 volts, to the contacts 48, 50, grounding the control gate CG and allowing the drain D to float erases a cell. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source S. Applying a negative voltage on the order of xe2x88x9210 volts to the control gate CG, applying 5 V to the source S and allowing the drain D to float can also erase the cell.
During the read operation, the signal from the cell being read (the xe2x80x9cselected cellxe2x80x9d SC) is compared to the signal from a reference cell, which is part of a reference cell array 51 as shown in FIG. 2, which array 51 is of generally the same size and configuration as the array 20. Similar to the array 20 of FIG. 1, the reference cell array 51 includes individual reference cells RC1, RC2, RC3, . . . RC32 made up of respective MOS field effect transistors T1, T2, T3, . . . T32, the transistors including a source S, a drain D, a floating gate FG, and a control gate CG. Bit lines B0-B7 and word lines W0-W3 are included, all as is well known. The cells are connected in an array of rows 52, 54, 56, 58 and columns 60, 62, 64, 66, 68, 70, 72, 74, with the control gates CG of the cells in a row (for example row 54) being connected to a respective word line (W1) and the drains D of the cells in a column (for example column 66) being connected to a respective bit line (B3). The sources S of the cells in a column are connected together, and are connected to the sources S of the cells of other columns by conductive lines (one shown at 78). Approximately every 20 bit lines across the array 51, each conductive line 78 connects to a contact (two shown at 80, 82) to which a voltage is supplied, to in turn supply a voltage to the source S of each transistor.
During reading of a selected memory cell of the array 20, electrical potentials are supplied to the source S (by means of applying voltage Vss to the contacts 48, 50), the drain D and the control gate CG of the selected cell as described above. Simultaneously, like electrical potentials are supplied to the source S (by means of applying voltage Vss to the contacts 80, 82), the drain D and the control gate CG of a reference cell of the array 20 (FIG. 2). The reference cells are fabricated so that when a memory cell of the array and a reference cell are simultaneously addressed, the addressed reference cell provides an output signal the level of which is generally between the levels of (i) the output signal of a programmed selected cell and (ii) the output signal of an erased selected cell. The output signals of the selected cell SC and reference cell RC are provided to a sense amplifier 84 (FIG. 3), and based on a comparison of the signals from the reference cell RC and the selected cell SC supplied to the sense amplifier 84, the sense amplifier 84 determines if the selected memory cell SC stores a logic 1 or a logic 0.
Again referring to FIG. 2, it will be noted that there is a resistance between each contact 80, 82 and the source S of each reference cell, the level of the resistance being substantially proportional to the distance from that reference cell to its associated contacts 80, 82. For example, for a reference cell RC13 positioned substantially midway between the Vss contacts 80, 82, the resistance between the source S of the reference cell RC13 and the contact 80 is 4R (four resistive units, i.e., four resistors 86, each with resistance R, in series), while the resistance between the source S of the reference cell RC13 and the contact 82 is also 4R (four resistive units, i.e., four resistors 86 each with resistance R, in series). During the read operation, this provides an overall resistance Rrc between the source S of the reference cell RC13 and the Vss contacts 80, 82 of:                                           1                          R              rc                                =                      xe2x80x83                    ⁢                                    1                              4                ⁢                R                                      +                                                        =                      xe2x80x83                    ⁢                      1                          2              ⁢              R                                                                                R            rc                    =                      xe2x80x83                    ⁢                      2            ⁢            R                                ⁢      1          4      ⁢      R      
Referring to FIG. 1, if the selected cell is also positioned substantially midway between the Vss contacts 48, 50, the resistance between the source S of the selected cell and its associated contacts 48, 50 substantially matches up with the resistance for the reference cell RC13 of the reference cell array 51. For example, for a selected cell C13 positioned substantially midway between the contacts 48, 50, the resistance between the source S of the selected cell C13 and the contact 48 is 4R (four resistive units, i.e., four resistors 86 each with resistance R, in series), while the resistance between the source S of the selected cell C13 and the contact 50 is also 4R (four resistive units, i.e., four resistors 86 each with resistance R, in series). During the read operation described above, this provides an overall resistance Rsc1 between the source S of the selected cell C13 and the Vss contacts 48, 50:                                           1                          R              sc1                                =                      xe2x80x83                    ⁢                                    1                              4                ⁢                R                                      +                                                        =                      xe2x80x83                    ⁢                      1                          2              ⁢              R                                                                                R            sc1                    =                      xe2x80x83                    ⁢                      2            ⁢            R                                ⁢      1          4      ⁢      R      
However, if the selected cell is positioned closer to one Vss contact 48, 50 than the other, i.e., closer to an edge of the array 20, the resistance between the source S of the selected cell and its associated contacts 48, 50 is substantially different from that of the reference cell RC13 described above. For example, during the read operation, while the resistance between the source S of the reference cell RC13 and the contacts 80, 82 is 2R, the resistance Rsc2 between the source S of the selected cell C16 (positioned close to an edge of the array 20) and the Vss contacts 48, 50 is:                               1                      R            sc2                          =                  xe2x80x83                ⁢                              1            R                    +                      1                          7              ⁢              R                                                                        1                      R            sc2                          =                  xe2x80x83                ⁢                                            7                              7                ⁢                R                                      +                          1                              7                ⁢                R                                              =                      8                          7              ⁢              R                                                                        8          ⁢                      R            sc2                          =                  xe2x80x83                ⁢                  7          ⁢          R                                                  R          sc2                =                  xe2x80x83                ⁢                                            7              ⁢              R                        8                    =                      .875            ⁢            R                              
which is quite different from 2R resistance between the source S of the reference cell RC13 and its associated contacts 80, 82. While the reference cell RC13 is well matched to a selected cell (C13) which is positioned substantially midway between contacts 48, 50 and provides a level of output signal which is substantially midway between the levels of (i) the output signal of a selected cell in its programmed state and (ii) the output signal of the selected cell in its erased state, this reference cell RC13 is not well matched to a selected cell (C16) which is near an edge of the array 20, i.e., which is substantially closer to one contact (48) than the other contact (50), in that the reference cell C13 does not provide an output signal the level of which is substantially midway between the levels of (i) the output signal of a selected cell in its programmed state and (ii) the output signal of the selected cell in its erased state. This is so because the resistance between each selected cell and the associated contacts 48, 50 may be different, while of course the resistance between the reference cell RC13 and its associated contacts 80, 82 remains the same, independent of which of the cells to be read is selected. Thus, the sense amplifier 86 may have difficulty in determining the state of the selected cell, i.e., whether such selected cell is in a programmed or erased state.
Therefore, what is needed is a method for improving the matching of source to Vss contact resistance of a selected cell and a reference cell.
In the present method of reading a memory cell of a memory cell array, electrical potentials are applied to a conductive structure connected to the drain, a conductive structure connected to the source, and the gate of the transistor of a cell to be read. Furthermore, electrical potentials are applied to a conductive structure connected to the drain, a conductive structure connected to the source, and the gate of the transistor of a reference cell, providing current through the reference cell. The level of resistance to current through the reference cell is selected from a plurality of levels of resistance.